Node topology employing command and data buffers for executing thread scheduling

ABSTRACT

The described embodiments include systems, methods, and apparatuses for increased efficiency processing flow. One method includes a plurality of stages configured to process an execution graph that includes a plurality of logical nodes with defined properties and resources associated with each logical node of the plurality of logical nodes, a recirculating ring buffer, wherein the recirculating ring buffer is configured to holding only any one of a control information, input, and, or out data necessary to stream a temporary data between each logical node of the execution graph, and a data producer, wherein the data producer is configured to stall from writing control information into a command buffer upon the command buffer being full, preventing command buffer over-writing.

RELATED APPLICATIONS

This patent application is a continuation of U.S. patent application Ser. No. 16/699,045, filed Nov. 28, 2019, which is a continuation of U.S. patent application Ser. No. 16/416,179, filed May 18, 2019, granted as U.S. Pat. No. 10,540,740 on Jan. 21, 2020, which is a continuation of U.S. patent application Ser. No. 15/450,959, filed Mar. 6, 2017, granted as U.S. Pat. No. 10,311,542, on Jun. 4, 2019, which are herein incorporated by reference.

BACKGROUND

Rendering synthetic 3D images commonly employs an algorithm for removing occluded or hidden surfaces. In the example illustrated in FIG. 1A, the yellow sphere obscures a portion of the blue sphere. When using a depth buffer style algorithm, the pixels that are nearest to the viewer, at the time the geometry is processed, update the final image. For example, if the geometry for the blue sphere is delivered prior to the yellow sphere, all of the pixels associated with the blue sphere will be written to the image, a portion of which will subsequently be overwritten by the yellow sphere. This extra work, that does not contribute to the final image, is called overdraw.

Rendering Intermediate Images

The process of rendering synthetic images also involves producing intermediate images, which are commonly used to represent various dynamic illumination effects. For example, generating shadows, reflections, specular lighting, and other contributions from global illumination models (see FIGS. 1A-1C). These effects are typically approximated using preliminary rendering passes, which capture illumination properties. The process of generating each of these intermediate images is known as a “render pass”. These images are then used as texture maps in subsequent render pass as indicated in FIGS. 1B and 1C. This is accomplished by rendering each such pass in the order presented by the application. This sequence is called Forward Rendering.

For example, consider shadow maps or projective shadowing whereby shadows are added to 3D synthetic image. If one looks out from a source of light, all of the objects seen will appear in light. Anything behind those objects, however, will be in shadow. This is the basic principle used to create a shadow map. The light's view is rendered into an intermediate image, thus storing the distance between the light source and every surface it sees (the shadow map). Later, the scene is rendered normally comparing the depth of every point drawn (as if it were being seen by the light, rather than the eye) to this shadow map. The images may also be referenced in a recursive manner, as seen by the Processed Shadow Map example in the previous figure.

Planar reflections are also produced using an intermediate image. The entire scene is rendered inverted. The scene is generally rendered with a wide field of view. During the final render pass the inverted reflection map is blended with the shiny planar surfaces, as shown on the floor of the previous figure. A tree or directed a-cyclical graph (DAG) of the dependencies between these images can be formulated, an example of which is shown in FIG. 2. Each of the intermediate images must be rendered in an order that meets these dependency requirements. Because these dynamically generated images will be sampled as texture maps in subsequent render passes at unpredictable locations, the entire image is rendered. Often a significant portion of the computation and power consumption required to render the final image is spent producing these intermediate images.

However, typically only a portion of these intermediate images contribute to the final image.

Computation and Power Saving Opportunities Stream Sorting

An opportunity exists to reduce the computation and power by eliminating the overdraw work associated with occluded pixels. Analysis indicates that 15-20% of the computation in a common benchmark is extraneous overdraw. However, traditional approaches to addressing this issue involve performing a depth sort prior to processing the pixels. In this way, only the pixels which are visible are actually processed. However, relatively large structures are required to store the unsorted pixels until all of the geometry that may influence the pixels is processed. When hardware is accelerating the depth sort process, these special purpose structures are integrated into the architecture and require significant area on the chip. The size of these structures is directly related to the quantity of geometry used to describe the scene. Hardware designers study the expected workloads for their device in order to select the optimal size of the structures.

Various forms of tile-based rendering are typically used in order to further reduce the size of these structures and provide the added benefit of significantly reducing memory bandwidth. Because the image is spatially partitioned into small rectangular regions, known as tiles, and further because only the geometry that may affect this portion of the image is processed, the size of the depth sorting structures may be reduced. When possible, the contents of the tile sized depth buffer and sorting structures are never written into memory, thus saving substantial memory activity.

Reducing the size of these structures is acutely important because under-sized structures result in significant performance and power penalties. If the capacity of the structures is exceeded all of the processing that has been performed to that point is discarded and must be restarted using less efficient mechanisms. Attempts to avoid a catastrophic capacity failure or minimize the penalty of a failure often involve synchronization and communication with software, also costing time and adding complexity. Because of a strong trend toward increasing geometry complexity in the future, existing hardware solutions continue to grow these structures. They do not provide a graceful degradation of performance and power consumption under stressful conditions. A solution which attempts to gain the benefit of eliminating overdraw, must also elevate the existing penalties associated with increasingly complex content.

The “Stream Sorting” mechanism presented below attains the power saving benefits of minimized overdraw, while eliminating the special purpose depth sorting structures and providing a graceful degradation of performance under stressful geometry loads.

Reverse Rendering

Opportunity also exists for significant power savings in the rendering of intermediate images. Rarely does all of the information generated in the intermediate images contribute to the final image. This is primarily due to the fact that the intermediate images are sparsely sampled. Consider the sampling charts of three shadow maps used in a popular benchmark, shown in FIGS. 3a-3c . When sampling is quantized to 4.times.4 blocks of pixels 13%, 55%, and 32% of the respective shadow maps contribute to the final image. Eliminating the extraneous work required to render the unused portions of the intermediate images provides an opportunity to reduce, and potentiality minimize, the overall computation and power consumption required to render the final image. In some cases, this excess work comprises 50% of the total computation.

The mechanisms proposed below capitalize on this opportunity and are collectively referred to as “Reverse Rendering”. Reverse Rendering, built upon Stream Sorting, significantly reduces computation and power consumption in a device.

Graph Execution

Stream Sorting and Reverse Rendering both depend on the ability of the architecture to configure the connectivity of the operations in a non-standard manner from a traditional rendering pipeline. These unique configurations are more generally termed a graph and apply to many more usage models than just those discussed here; for example, computer vision algorithms are particularly amenable to this capability, as can be seen in FIGS. 4A and 4B. An understanding of the approach employed by present architectures is helpful in understanding the significance of this invention.

Existing fixed rendering pipeline architectures simulate arbitrary graph execution by treating their existing fragment shader unit(s) as a single node in the graph. The device is programmed to perform a single operation. The input and output data associated with the processing node are stored in memory. In this manner, the entire graph can be simulated, by programming the first node, processing all of the input data from memory and writing the output data for that node to memory. The device is then reprogrammed for the second node's operations, the output data from the previous node's buffer is read back from memory, computations are performed for the second node and the results are written to memory. This procedure continues until all nodes in the graph have been processed. Two key disadvantages of this approach are important. First, the often-temporary data communicated between interior nodes is stored in memory, requiring significant power. Secondly, the CPU often must synchronize with the device in order to reprogram it for the next node's operations, costing time and power.

SUMMARY

A system for reducing power consumption, memory transactions and computation in graphics rendering, wherein the said system is caused to perform computations which contribute to a final image, which computations comprise rendering the image in reverse order wherein the said rendering further comprises projecting a plurality of texture coordinates from a current image back into a dependent image. The said computations further comprise performing a delayed visibility sort operation, filtering a computed plurality of pixel values; and projecting the computed pixel values comprised in the final image.

In a system for reducing power consumption and computation in graphics rendering, a method comprising performing of computations which contribute to a final image, which computations comprise rendering the image in reverse order wherein the said rendering further comprises projecting a plurality of texture coordinates from a current image back into a dependent image. The said computations further comprise performing a delayed visibility sort operation, filtering a computed plurality of pixel values; and projecting the computed pixel values comprised in the final image.

Stream Sorting and Reverse Rendering both depend on the ability of the architecture to configure the connectivity of the operations in a non-standard manner from a traditional rendering pipeline. These unique configurations are more generally termed a graph and apply to many more usage models than just those discussed here, as would be apparent to a person having ordinary skill in the art.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-C illustrates an embodiment of rendered synthetic 3D images.

FIG. 2 illustrates rendering of intermediate 3D images.

FIGS. 3a-3c further illustrate via a graphics, rendering of intermediate images.

FIGS. 4a-4b illustrates reconfigurability for a traditional 3D pipeline and for Scale Invariant Feature Transform (SIFT).

FIG. 5 illustrates Stream Sorting and Reverse Rendering utilizing an alternate rendering pipeline.

FIG. 6 illustrates reverse rendering using display list-based approaches.

FIG. 7 illustrates reverse rendering using tile-based display list approaches.

FIG. 8 illustrates reverse rendering using texture coordinate storage approaches.

FIG. 9 illustrates a draw buffer approach.

FIG. 10 illustrates generating a draw buffer.

FIG. 11 illustrates dynamic memory objects.

FIG. 12 illustrates rendering with a draw buffer.

FIG. 13 illustrates via a table, triangle index re-sequencing.

FIG. 14 illustrates line delineated block compression.

FIG. 15 illustrates compression blocks.

FIG. 16 illustrates pre-marking of tiles that potentially contribute to the final image, by processing only the vertices for each render pass in reverse order.

FIG. 17 illustrates a topology of node resources.

FIG. 18 illustrates an alternative topology of node resources.

FIG. 19 illustrates a sub-system block diagram.

FIG. 20 illustrates a block diagram according to an embodiment of the invention.

FIG. 21 illustrates a process flow diagram of the producer and consumer.

FIG. 22 illustrates a method flow of the invention.

FIG. 23 illustrates resources/properties associated with a node or nodes, and their respective functions.

FIG. 24 illustrates a cache line read request that includes an address as usual, but also includes additional fields.

FIG. 25 illustrates the size of a super-page and the entire layer which effectively provide strides that are used to address individual cache lines.

FIG. 26 illustrates operations of an example embodiment.

FIG. 27 illustrates a table of draw call sequence ranges provided to hardware.

DETAILED DESCRIPTION

Architecture

A uniquely flexible and programmable architecture enables Stream Sorting and Reverse Rendering in a particularly efficient manner. Although this architecture is not the only method whereby Stream Sorting and Reverse Rendering may be implemented, nor are they exclusively dependent on this architecture, it provides an efficient framework for their implementation.

Flexible Processing Nodes

An embodiment of the system includes an architecture which comprises a plurality of logical nodes comprised in a single or plurality of stages, and connected together in an arbitrary topology. While the said nodes are logical, the stages are physical and each stage is capable of servicing multiple nodes. Preferably, the stages comprise means for providing strict ordering and data dependency tracking. Specific properties and resources are associated with each node. Many of the resources associated with a node have specific hardware support, which improves their behavior. For example, values from the Constant buffers are prefetched. These properties and resources provide each node with tremendous flexibility for performing graphics related tasks or more general-purpose operations. These properties further can provide each said node with flexibility for performing other applications like computer vision, video and image processing, high performance data parallel computing, etc. Other variations are possible and even desirable, as would be apparent to a person having ordinary skill in the art. An example embodiment, shown in FIG. 23, illustrates resources/properties associated with a node or nodes, and their respective functions.

Special Purpose Nodes

For performance reasons, certain operations may require specialized fixed function hardware, such as a Rasterizer. Other special operations, such as texture sampling and various mathematical operations are not exposed as nodes, but are accessible directly through instructions. These special purpose modules conform to the same interface requirements as the other more flexible nodes, thus allowing them to seamlessly integrate into a consistent and homogeneous architecture.

Inter-Node Communication

Execution commands and synchronization between nodes is accomplished through Command buffers, while data is delivered through Input and Output buffers. Importantly, all control information and input/output data is delivered through buffers, which have a memory image. The architecture essentially retains no device state exclusively in registers on chip. This includes both internal and external control, which are formulated as commands sent between the nodes.

The input and output data, which is communicated between nodes, is similarly delivered through memory buffers; however, these buffers are managed by the device so as to be much smaller than would be required if the entire output from a node were stored in memory. The buffers are treated as ring-buffers, which utilize addressing that wraps to the beginning of the buffer once the end has been reached. Because the buffers need only hold sufficient data to stream the temporary data between nodes in the graph, the buffers often reside in the on-chip caches, greatly reducing the power consumption associated with DRAM memory transactions.

The data in the caches may also be explicitly invalidated using either commands placed in the command buffer or instructions placed in the programs. The caches may be selectively invalidated for all data contained within a rectangular area in a single clock cycle. This explicit invalidate mechanism provides increased control over the memory hierarchy and results in reduced power consumption.

The memory buffer approach enables low latency context switches that are fully pipelined. No sequential load/unload of the current context is required. Multiple contexts may operate concurrently in the device.

A Context

According to an embodiment, a particular combination of nodes, with their properties and resources defined, that are connected in specific topology and bound to an initial command buffer, form a “Context”. Different Contexts may be defined to perform 3D rendering for particular specifications. For example, a simple Context can be defined to support the OpenGL ES 2.0 standard, while a different Context might also be defined for the DirectX 11 specification, which contains several more stages. Significantly, Contexts may also be defined for non-rendering-based problems, such as the Scale-Invariant Feature Transform (SIFT), a common computer vision operation for recognizing objects. FIGS. 4A and 4B demonstrate this reconfigurability for a traditional 3D pipeline and for Scale-Invariant Feature Transform (SIFT).

These architectural decisions result in the several advantages over more traditional 3D rendering hardware and are of particular value for Stream Sorting and Reverse Rendering. Embodiments disclosed include flexible nodes or stages, allowing for varied and programmable functionality. Custom contexts allow for a single or plurality of alternate rendering pipelines, and multiple concurrent contexts allow for sharing of compute resources while performing different tasks. Applying these concepts to the power and compute saving opportunities described above is the primary focus of the remainder of this document.

Stream Sorting

Stream Sorting and Reverse Rendering utilizes an alternate rendering pipeline, shown in FIG. 5. The pipeline is divided into three phases entitled XY Sorting, Depth Sorting and Rendering.

XY Sorting Phase

The purpose of the XY Sorting phase is to sort the streams of triangles into a collection of Tile Display Lists. Each list is actually a Command buffer, as described in the section “INTER-NODE COMMUNICATION” above, which identifies the geometry that potentially modifies the content of the tile.

The vertices need to be transformed into screen space in order to perform the triangle-tile intersection test. This is accomplished by executing a factored version of the Vertex Shader and Triangle Processor kernels, which computes only the position related outputs. Typically, back-facing triangles, and other clipped or non-visible triangles, are discarded at this point.

The original index into the vertex buffer, for each vertex of a triangle, is forwarded through the Triangle Processor to the Rasterizer. The Rasterizer then iterates over the triangle to determine which tiles it intersects. A command referencing the original vertices is inserted in the Command buffer for each intersecting tile. This allows the original vertex buffer to be used in subsequent phases and eliminates the need to write out the transformed vertices and their new indices. This results in additional computation, but saves memory bandwidth.

Once all of the geometry has been sorted, the individual Command buffers are passed onto the next phase. However, if the Command buffer for a particular tile becomes full the buffer is simply processed immediately. This simple solution avoids the complexities associated with attempting to expand the Command buffer size or chaining it to another buffer. It also avoids the latency of a software interrupt, if memory pages aren't available for buffer expansion. With the ability to define an alternate rendering pipeline, the complexities and performance penalties are simply avoided.

Depth Sorting Phase

The Depth Sorting phase performs the traditional hidden surface depth test to determine which triangles potentially influence the final image. This is accomplished by processing each Tile's Display List (the tile's Command buffer) using the same position factored versions of the Vertex Shader and Triangle Processor kernel. The Rasterizer then iterates each triangle, performing the per pixel depth test. Any triangle which passes the depth test will be written into the output Command buffer. It is possible for triangles to be written into the output Command buffer that do not actually contribute to the image. This occurs when the geometry is processed back to front. However, the depth test performed in the Rendering phase will discard any pixels that do not ultimately contribute. Finally, when applicable, a Reverse Rendering Draw Buffer, which identifies contributing triangles, is generated in this phase for intermediate images rather than the output Command buffer. This buffer and its usage is described in detail in a subsequent section.

Rendering Phase

The rendering phase processes the Command buffer from Depth Sorting phase as the contributing triangles are identified for the tile. In this manner, the triangles are streaming into the Rendering phase. The complete Vertex Shader and Triangle Processor kernel are executed. Because the fully updated depth buffer is still resident in the cache, the depth test performed in the Rasterizer will be efficient. It will also limit the pixel processing to only those pixels which contribute to the image.

Stream Sorting has eliminated unnecessary pixel processing due to object occlusion and contained the depth buffer memory bandwidth to on-chip caches, thus significantly reducing the power consumption of the device.

Reverse Rendering

Reverse Rendering is the general concept of rendering the final image first while recursively projecting backward into the intermediate images and rendering only those portions which contribute. Several mechanisms for realizing this benefit, within the context of 3D rendering hardware and software, are presented. The somewhat simple approaches described in the initial sections provide the foundational concepts for the increasingly more efficient techniques which follow.

1.1 Display List Based Approaches

A display list consists of multiple Draw commands, which describe the triangles to be rendered to the current image. Additionally, the display list contains state changes and bindings to various resources, such as constants and texture maps. The color of each pixel in an image can be traced back to one or more triangles in the display list and their state bindings. Individual pixel values may be computed by processing a subset of the display list and by constraining the image updates to the pixels of interest. The first approach is somewhat simplified, ignoring Stream Sorting, but provides the foundational concepts for the remaining approaches.

1.1.1 Complete Display List Approach

FIG. 6 illustrates the complete display list approach in an embodiment. The application, that assembles the display list and its' state, delivers the commands to a software driver through a standardized application interface. The driver retains the display lists for later processing without servicing the commands. When the final image's display list is presented to the driver immediate mode rendering proceeds normally, with one exception. The SAMPLE instructions, embedded in the pixel and vertex shading programs of a traditional 3D rendering pipeline, must not trivially sample a dynamically rendered intermediate image, because the necessary pixel values may not yet have been computed.

The Sampler unit in the hardware, which services the SAMPLE instructions as is shown below, verifies that the sample location in the bound texture map contains valid data. The filtering neighborhood, along with the sample location provides the area of the intermediate image that needs to be valid. This is accomplished by managing a simple memory resident bit-map of valid pixels. If the pixels are valid then the Sampler proceeds normally. However, if all of the needed pixels are not valid then the Sampler proceeds to insert new work into the pipeline, such that the pixel values will be computed. Once this is completed the bit-map of valid pixels is updated.

When the pixel values need to be computed the display list for the intermediate image, referenced in the SAMPLE instruction, is processed through the Vertex Shader, Triangle Processor and Rasterization stages to determine which triangles intersect the needed pixels. Only the triangles of interest are passed to the Pixel Shader stage. Pixels are further constrained to lie within the region identified by the sample location and the filter neighborhood. In this manner, the pixel processing is performed for only those pixels which are sampled by the current image.

Finally, the Stream Sorting mechanism eliminates overdraw in the current image, such that only the contributing pixels are computed in the intermediate image, thus minimizing the computation and power consumption requirements.

However, processing the entire display list down through the Rasterization stage for each SAMPLE instruction is extremely inefficient. The next section addresses this issue.

1.1.2 Tile Based Display List Approach

Tile based rendering divides an image into many rectangular regions, called tiles, and pre-sorts the triangles in the original display list into separate smaller tile display lists, based on the tiles they intersect. This is accomplished by processing the display list, typically just the vertex position information, through the Vertex Shader and Triangle Processor. At this point in the pipeline the screen space positions of the triangles are known and the tile display lists are generated. These lists often reference the original display list for the remaining vertex attributes. They may also contain or reference additional temporary information, such as various geometry gradients, in order to save future computation.

The process of Reverse Rendering is much the same as the Complete Display List approach above, except that only the intersecting tile's display lists need be processed. For example, as is shown in FIG. 7, two tile display lists would be processed, because the sample location and filter neighborhood, identified by the blue square in the intermediate image, intersects two tiles. This approach significantly reduces the geometry processing load.

The tiles may also be pre-marked as potentially contributing to the final image, by processing only the vertices for each render pass in reverse order, as shown in FIG. 16. Any pixel shader operations on dependent texture coordinates must be appended to the vertex shader. The vertices of each triangle form a bounding area, for which all intersecting tiles are marked as being needed. Only triangles who's fragment shaders access dependent textures and who themselves lie within previously marked tiles need be processed. This process proceeds recursively through each render pass; after which, the marked tiles' display lists are rendered in the normal stream sort manner.

These approaches are not optimally efficient because the size of the tiles is typically much larger than the size of the filter neighborhood, which results in potentially unnecessary computation. However, reducing the tile size increases the overhead cost of the tile display lists.

1.2 Texture Coordinate Storage Approach

An approach which stores the texture coordinates that are used to sample an intermediate image is depicted in FIG. 8. In this approach the pixel shader is divided into segments based upon the location of the SAMPLE instructions which sample an intermediate image. In a multi-pass manner, the draw-calls for the current image are reissued, each time with the next segment of the pixel shader appended. However, in between each pass the Display List for the referenced intermediate image is processed, checking that the pixel locations of the triangles fall within the areas specified by the list of texture coordinates. These areas are indicated by the small blue squares in the diagram. In this way, only the areas of the intermediate image that will be sampled in the next pass of the current image are computed.

This approach does not switch between the current image and the intermediate image as frequently, which reduces the cost of hiding the latency between switches. Caches can be reduced in size with this approach; however, the bandwidth costs of storing and searching the list of texture coordinates is quite high.

1.3 Draw Buffer Approach

An approach which minimizes both the cost of identifying the specific triangles that contribute to a pixel and retains fine granularity of the computation size, employs a new structure called a Draw Buffer. A Draw Buffer is a sparse, three dimensional, dynamically sized, memory resident structure, which provides references to the contributing triangles for each pixel in an image. FIG. 9 shows an example image with specific pixels labeled A and B. Pixel A's value is determined solely by a single triangle from the display list. The Draw Buffer contains a reference to this triangle. Conversely, pixel B's value is determined by the contributions of three triangles, typically due to blending between the triangles. The Draw Buffer contains references to all three triangles in a specified order. The Draw Buffer replaces the functionality of the display lists in the approaches from above.

1.3.1 Generating a Draw Buffer

When processing an intermediate image, a Draw Buffer is generated at the output of the Rasterizer node, as shown in FIG. 10. Opaque primitives over write the list of contributing triangles in the Draw Buffer, while translucent primitives append their triangle ID to the list. A hardware mechanism for dynamically managing the storage of data in a Draw Buffer is important to reduce its memory size.

1.3.1.1 Dynamic Memory Objects

FIG. 11 shows a dynamic memory object, addressed as a three-dimensional entity, where the last dimension is dynamically and sparsely allocated by the hardware. Each layer consists of a two-dimensional array of super-pages. A super page is a collection of virtually contiguous pages, as shown at the bottom of FIG. 11. The dashed line rectangles shown in the first layer of the diagram each represent a super-page. The cut-away reveals sparsely allocated pages for each layer of a super page at several different locations. For example, point A lies within a super-page which has three layers, while B contains five layers. At locations C and D two layers and four layers are allocated, respectively.

A cache line read request includes an address as usual, but also includes additional fields, shown in FIG. 24 The Super-Page address is the traditional cache line address, while the Page Index selects the specific page within the super-page. Finally, the Layer Index selects the appropriate layer within the object.

A few additional fields are also needed to compute the complete address within the object. The size of a super-page and the entire layer effectively provide strides that are used to address individual cache lines, shown in FIG. 25.

Additional memory operations are supported on dynamic memory objects, which provide support for more advanced operations, such as initializing memory and appending pages to the sparse structure.

The operations of an example embodiment, shown in FIG. 26, require specific hardware support. The process of allocating a new page is handled completely by hardware. Initially a sufficient number of pages are obtained, from a pool of available physical pages, for super-pages. The Translation Table entry for the first page of the first layer is read to obtain the number of layers currently allocated. The number is stored in the lower bits of the physical address. This number is incremented. The physical addresses for each of the pages within the super-page are copied to the last layer and the new pages are written to the first layer. In this way, the layers are ordered except for last layer, which is always stored in the first physical layer. This provides a mechanism such that the append operation requires only two memory transactions in the Translation Table. Read and write operations also utilize the layer count to determine if a request is out of bounds.

Dynamic memory objects provide significant memory foot-print benefits for Draw Buffers.

1.3.2 Rendering with a Draw Buffer

During Reverse Rendering, the execution of a SAMPLE instruction produces the same valid pixel check in the Sampler Unit as previous approaches, although the valid bits are stored in the Draw Buffer. When additional computation is required, only the contributing triangles are processed. The Draw Buffer's triangle indices reference the tile display list, which also references the original display list. The contributing triangles are inserted into the pipeline in the order specified by the Draw Buffer. Only the necessary pixel values are computed. The newly computed pixels are then sampled, filtered and returned to the shader program. This fine-grained approach reduces the amount of unnecessary geometry processing, while also minimizing extraneous computation of pixel values in the intermediate image. Another advantage of computing the pixel values just prior to their usage by the Sampler Unit is that it is very likely to be resident in the cache, and will not require a memory transaction and the power consumption that such a transaction entails.

The Draw Buffer approach provides a significant improvement over the previously considered approaches as is shown in FIG. 12. However, because this approach fundamentally trades-off increased memory bandwidth for computational efficiency, mechanisms for compressing the Draw Buffer are now considered.

1.3.3 Draw Buffer Compression

Storing a draw-call index and a triangle index in each element of the Draw Buffer is a simple structure that provides relatively direct access to the display list. A 16-bit value can safely be used for the draw-call index; however, a 32-bit value is required for the triangle index. Naively storing 48-bits per element in a fixed multi-dimensional array is unlikely to be acceptable, because of the large memory foot print and bandwidth.

1.3.3.1 Triangle Index Resequencing

According to an embodiment, a mechanism for assigning a frame level sequence number or ID to each triangle is helpful, because it can frequently be stored in 16-20 bits. The necessary precision can be determined in advance by the driver. However, an inverse translation function is required, which will convert back to a draw-call offset and triangle index. This is accomplished by providing the hardware with a table of draw call sequence ranges, similar to that shown in FIG. 27. This table is searched to find the draw-call containing the triangle sequence number and the residual value becomes the triangle index number. The Display List Offset column provides the relative starting location for the state bindings and the draw-call commands within the display list. This simple re-sequencing technique typically provides a 3:1 compression ratio.

1.3.3.2 Block Based Compression

Draw Buffers generally benefit from block-based compression techniques, because of significant coherency among the triangle Id's. Analysis has shown that for scene based intermediate images, approximately 75% of all 8.times.8 blocks contain only two unique triangle Id's. However, certain geometrically dense intermediate images, such as shadow maps, which tend to be projected from articulated figures, contain many more unique triangle Id's. This bimodal behavior suggests a hybrid mechanism is therefore preferable, where an opcode identifies the type of compression employed by each block. An 8.times.8 block is assumed for the following compression methods.

Line Delineated Block Compression

When it has been determined that a block is bisected by a single line (FIG. 13) with all of the pixels on one side of the line originating from one triangle and similarly on the other, a highly efficient compression technique may be utilized according to an embodiment. This technique may also be employed when the block is completely covered by a single triangle. The compressed block may be encoded in a manner similar to the layout shown in FIG. 14. An Opcode identifies the type of compression utilized on the block. Four Valid bits specify which quadrants of the 8.times.8 are valid and thus encoded. Two 16-bit Triangle Id's are stored in half of the compressed block. The remaining fields describe the slope and position of the bisecting line. The X field indicates that the slope is increasing in the x direction faster than in the y direction. The Edge field identifies the edge from which the Intercept and Slope values originate. Identifying the specific intercept edge reduces the precision requirements for Slope field. When usable, this mechanism provides a 16:1 compression ratio.

Golomb/Rice Variable Length Coding

A lossless compression technique is employed for more complex blocks. The usual Opcode and Valid fields are present, along with a Size field indicating the size, in 64-bit words, of the variable length block. The Base Triangle ID provides the starting value for the Golomb/Rice encoded delta values. The Mode (Md) field indicates the k value (the number of unencoded least significant bits) between two optimally chosen values. This form of encoding typically produces approximately a 4:1 compression ratio.

Compression of the Draw Buffer is important for reducing the overall bandwidth associated with Reverse Rendering and achieving the desired power savings.

1.3.4. Buffer Clearing

With the use of a Draw Buffer the clear operation is not required. The zero triangle ID is reserved to indicate a cleared pixel value is stored in the image; however, the actual value need not be written because the Draw Buffer carries the needed information. The clear value for each intermediate image is stored in state and returned to the sampler directly, without passing though memory. The result returned from the sampler will simply be the state clear value.

The four basic approaches discussed for performing Reverse Rendering generally increase in complexity, but also the degree to which power consumption is reduced. It is conceivable that a path through multiple approaches may be traversed in order to achieve the most optimal solution as would be apparent to a person having ordinary skill in the art.

With Stream Sorting eliminating overdraw and Reverse Rendering eliminating unnecessary computation in intermediate images the power consumption required to render modern synthetic 3D images is dramatically reduced. Additionally, the bandwidth savings afforded by Stream Sorting also significantly reduces power consumption.

Referencing back to intra-node and inter-node communication, an example of a node topology is illustrated in FIGS. 17 and 18. In particular, FIGS. 17 and 18 both illustrate computational nodes 1710, 1810 at any topological layer in a hierarchical structure. Both figures show a topology consisting of four computational nodes 1710, 1810, however, any number of nodes may be possible—in any number of topological layers, and any type of hierarchical structure.

Still in reference to FIGS. 17 and 18, illustrated are a system comprising a plurality of logical nodes 1710, 1810 comprised in a single or plurality of stages, with defined properties and resources associated with each node 1710, 1810, for reducing compute resources. In an exemplary embodiment, the system may further comprise: at least a recirculating ring buffer holding only any one of a control information, input, and, or out data necessary to stream a temporary data between node 1710, 1810 and, or nodes 1710, 1810 in an execution graph, thereby reducing size of said recirculating ring buffer. Control information may reside in a recirculating ring command buffer 1730, 1830—index pointing to the appropriate recirculating ring data buffer 1720, 1830. The control information may also control and coordinate the intra-node staging and inter-node synchronization. The input and out data are data residing in the recirculating ring data buffer 1720, 1830 are involved in executing the graph tasks.

Preferably, the recirculating ring buffer being sufficiently reduced in size to reside in an on-chip cache, such that any one of the control information, input, and, or out data between node and, or nodes need not be stored in memory. In a preferred embodiment, the recirculating ring data buffer 1720, 1830 may contain just a sufficient amount of input and, or out data in order to execute any prescribed task and reside within an on-chip cache. In alternative embodiments, the recirculating ring command buffers may also be small enough to fit on an on-chip cache, and not reside within memory.

Moreover, as FIG. 18 illustrates—alternatively—a recirculating ring buffer may contain both control information and input and, or out data. These recirculating ring buffers are hybrid-type buffers—having structural and functional characteristics of both recirculating ring data buffers and recirculating ring command buffers 1830.

While not shown in FIG. 17 or 18, the control information may further comprise a command related to invalidating any one of the input and, or out data held in a recirculating ring data buffer, clearing the buffer of tasked data. This type of cache clearing mechanism results in lower latency and improved data throughput due to its lowered memory transaction. An additional pathway for lowered latency and improved data throughput may be a mechanism providing for a producer, which stalls from writing any more control information into a recirculating ring command buffer, upon the buffer being full. This may ensure preventing command buffer over-writing, and thereby also reducing compute resources associated with a DRAM memory transaction.

While also not shown in FIGS. 17 and 18, simple addressing schemes may be used to route the data messages through nodes and between nodes, without the need for transactionally expensive routing tables or other complex schemes. For example, in some embodiments, the recirculating ring buffer utilizes addressing that wraps to the beginning of the recirculating ring buffer once the end has been reached.

Moreover, the node topology may comprise a variety of processor configurations: different nodes sharing a processor; different nodes with different processors. In some embodiments, a node topology may comprise of a hybrid topology, wherein some nodes include different processors, while the remaining nodes include uniform processing. Furthermore, multiple graph task executions may occur concurrently, thereby not requiring a sequential stage-stage and, or node at a time processing. In addition to the variety of topology configurations and processing paradigms, the on-chip/off-chip caches, in addition to the actual recirculating ring buffers, may vary in size—for both the recirculating ring command buffers and the recirculating ring data buffers.

Now in reference to FIG. 19, illustrated is a system diagram depicting a system comprising a plurality of logical nodes comprised in a single or plurality of stages, with defined properties and resources associated with each node, for reducing compute resources, said system further comprising: at least a recirculating ring buffer 1910, 1930 holding only any one of a control information, input, and, or out data necessary to stream a temporary data between node and, or nodes in an execution graph, thereby reducing size of said recirculating ring buffer 1910, 1930; the recirculating ring buffer 1930 being sufficiently reduced in size to reside in an on-chip cache 1920, such that any one of the control information, input, and, or out data between node and, or nodes need not be stored in memory.

In a preferred embodiment, the control information further comprises a command related to invalidating any one of the input and, or out data held in a recirculating ring data buffer 1930, clearing the buffer 1930 of tasked data; and a producer is stalled from writing any more control information into a recirculating ring command buffer 1910 upon the buffer 1910 being full, preventing command buffer over-writing, and thereby reducing compute resources associated with a DRAM memory transaction.

These problems with content management and buffer traffic are eliminated in part by making small enough the recirculating ring data buffer 1930 to fit into a portion of either the on-chip cache 1920. This eliminates instances of clogging or over-write and reduces traffic or bottlenecking to main memory. Furthermore, clearing of recirculating ring data buffers 1930 occurs when the processor 1940 completes the graph task associated with the buffer 1930. This leads to less processor 1940 stalls and substantially less memory overhead, since processors do not need to perform a “validating reads”. Validating reads will fetch data from the on-chip cache 1920, instead of from the memory, reducing latency; increasing bus bandwidth; and improving overall data throughput.

In continuing reference to FIG. 19, a producer is stalled from writing any more control information into a recirculating ring command buffer 1910 upon the buffer 1910 being full, preventing command buffer over-writing, and thereby reducing compute resources associated with a DRAM memory transaction. This buffering mechanism in a multi-level hierarchy avoids the “over-writing” issues—and the associated latency—that usually plague the larger cache-based ring buffers.

In a further embodiment, additional limitations may be interrelated with the on-chip cache, memory, and processor. While not shown in FIG. 19, the system may further comprise a buffer management module. The buffer management module may further comprise a read pointer queue in operable communication to a write pointer queue via a cache gauge. The additional limitations may enhance management of the buffer content and traffic throughout the multi-hierarchical network. Disclosed is a system to employ re-circulating ring buffers to reduce computing power, said system comprising of: at least a set of logical nodes, wherein said nodes are further comprised in a single or a plurality of stages, connected together in an arbitrary topology; at least one recirculating ring buffer, said buffer further comprising any one of at least a control information, input and, or out data delivering temporary data between said stage and, or said node in an execution graph, such that any one of the control information, input, and, or out data between node and, or nodes need not be stored in memory; a buffer management module, said module managing buffer content and traffic via a write pointer queue and a read pointer queue, operably coupled via a cache gauge.

In a preferred embodiment, the read pointer queue alerts a cache gauge of an impending completion of a graph task and, or a maximum capacity of any one the recirculating ring buffer and the cache gauge updates the write pointer queue to prepare for a producer stall and, or a buffer clear.

The anticipation for a producer stall and, or a buffer clear in the multi-dimensional hierarchical network can further eliminate system overhead in order to minimize latency/power consumption. For example, a system implementing the buffer management module may be able to redirect and allocate resources as per the impending completion of graph tasks and, or maximum capacity of any one of the recirculating ring buffers based on any one of the reads of the read pointer queue, cache gauge, and, or write pointer queue updates.

FIG. 20 shows a process flow of an embodiment of the invention. FIG. 20 shows the diagram of a hardware managed command buffers. A node 2011, 2013, 2015 connects to one command buffer 2010, 2012, 2014 at the input. A set comprising of a node, a command buffer and a recirculating ring data buffer are connected. The re-circulating ring data buffers are small enough to fit on on-chip caches 2020. Alternatively, the re-circulating ring data buffers may fit on off-chip caches. Each such set is connected to another set and forms a chain of command buffers. Node 2011 is connected to a command buffer 2010 at the input. Node 2011 receives a command to the re-circulating ring data buffer 2016, 2017, 2018 from command buffer 2010. The command buffers are efficiently managed by the scheduler. Once the commands for a node is read, the contents of the command buffer 2010, 2012, 2014 are no longer required, and hence the command buffers can be overwritten.

Further yet, in an embodiment of the invention, the re-circulating ring data buffers can be implemented in a FIFO (first in, first out) method. Once data for all instances of a node is read, the contents of the input data buffer are invalidated 2019, so the re-circulating data buffer 2016, 2017, 2018 can be overwritten. In a continuing reference, multiple graph task executions may occur concurrently, thereby not requiring a sequential stage-stage and, or node at a time processing.

FIG. 21, is a process flow diagram according to an embodiment of the invention. With reference to FIG. 21A, in an exemplary embodiment of the invention, the recirculating ring buffer is a command buffer 2103, whereby commands are written 2102 into the recirculating ring buffer 2103 by a producer 2101 and commands are read 2105 by a consumer 2104. Additionally, in an embodiment of the invention, the producer 2101 may stall the writing of commands 2102 on the command buffers 2103 to prevent overriding 2106.

In yet another embodiment of the invention, the writing 2102 of input and, or out data is by updating a write-only pointer in a context buffer by the producer 2101; and the reading 2105 of input and, or out data is by processing a read-only pointer in a context buffer by the consumer 2104. The context buffer may be prefetched. The size of the task context buffer may vary.

Further yet, now in reference for FIG. 21B, in another exemplary embodiment of the invention, the input data and, or out data is written 2102 by a producer 2101 and read 2105 by a consumer 2104, whereby the producer 2101 and consumer 2105 are closer in a memory hierarchy due to the input data and, or out data held in the recirculating ring buffer 2107 residing in the on-chip cache. Once, the task is complete, and the re-circulating ring data buffers residing on the on-chip caches are full, the control information may further instruct a command related to invalidating 2108 the input and, or out data held in a recirculating ring data buffer, clearing the buffer of tasked data. This kind of cache clearing mechanism leads to a lower latency and improved data throughput due to its lowered memory transaction.

Further yet, in another embodiment of the invention, an additional pathway for lowered latency and improved data throughput may be a mechanism providing for a producer 2101, which stalls 2106 from writing any more control information into a recirculating ring command buffer 2107, upon the buffer being full. This may ensure preventing command buffer overwriting, and thereby also reducing compute resources associated with a DRAM memory transaction thus, improving latency.

In a continuing reference, to FIGS. 21 A and B, the writing of informational control data may be accomplished by updating a write-only pointer in a context buffer by the producer 2101; and the reading of informational control data by processing a read-only pointer in a context buffer by the consumer 2104. Further yet, the context buffer may be prefetched and the size of the task context buffer may vary. Alternatively, multiple contexts may operate concurrently in a device.

In a continuing reference, in an embodiment the recirculating ring buffer utilizes addressing that wraps to the beginning of the recirculating ring buffer once the end has been reached. Because the buffers need only hold sufficient data to stream the temporary data between nodes in the graph, the buffers often reside in the on-chip caches, greatly reducing the power consumption associated with DRAM memory transactions.

FIG. 22 illustrates a method comprising a plurality of logical nodes comprised in a single or plurality of stages, with defined properties and resources associated with each node, for reducing compute resources, said method comprising the steps of: (1) holding only any one of a control information, input, and, or out data necessary to stream a temporary data between node and, or nodes in an execution graph in any one of a recirculating ring buffer, thereby reducing size of said recirculating ring buffer 2101; (2) residing said recirculating ring buffer in an on-chip cache, such that any one of the control information, input, and, or out data between node and, or nodes need not be stored in memory 2102; (3) invalidating any one of the input and, or out data held in a recirculating ring data buffer, clearing the buffer of tasked data 2103; and (4) stalling a producer from writing any more control information into a recirculating ring command buffer upon the buffer being full, preventing command buffer over-writing, and thereby reducing compute resources associated with a DRAM memory transaction 2104.

Since various possible embodiments might be made of the above invention, and since various changes might be made in the embodiments above set forth, it is to be understood that all matter herein described or shown in the accompanying drawings is to be interpreted as illustrative and not to be considered in a limiting sense. Thus, it will be understood by those skilled in the art that although the preferred and alternate embodiments have been shown and described in accordance with the Patent Statutes, the invention is not limited thereto or thereby.

The figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present invention. It should also be noted that, in some alternative implementations, the functions noted/illustrated may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

In general, the steps executed to implement the embodiments of the invention, may be part of an automated or manual embodiment, and programmable to follow a sequence of desirable instructions.

The present invention and some of its advantages have been described in detail for some embodiments. It should be understood that although some example embodiments of the stream sorting and reverse rendering mechanism, system, and method are described with reference to 3-dimensional graphics processing, the system and method is highly reconfigurable, and embodiments include reconfigurable systems that may be dynamically adapted to be used in other contexts as well. It should also be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. An embodiment of the invention may achieve multiple objectives, but not every embodiment falling within the scope of the attached claims will achieve every objective. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. A person having ordinary skill in the art will readily appreciate from the disclosure of the present invention that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed are equivalent to, and fall within the scope of, what is claimed. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. 

The invention claimed is:
 1. A machine configured for increased efficiency processing flow, comprising an arrangement of: a plurality of stages configured to process an execution graph that includes a plurality of logical nodes with defined properties and resources associated with each logical node of the plurality of logical nodes; each stage comprising: a command buffer, wherein the command buffer comprises a recirculating ring buffer holding control information; data buffers, wherein the data buffers comprise recirculating ring buffers holding input, and, or output data necessary to stream a temporary data between each logical node of the execution graph; and a data producer, wherein the data producer is configured to stall from writing control information into the command buffer upon the command buffer being full, preventing command buffer over-writing, which prevents the data buffers from being over-written.
 2. The machine of claim 1, wherein the control information further comprises any of, or combination of, an execution command and, or a command related to synchronization between the logical nodes.
 3. The machine of claim 1, wherein invalidation of data of the command buffer or the data buffers is based on completion of processing a graph task.
 4. The machine of claim 1, wherein the command buffer and the data buffers that hold input data and, or out data reside in on-chip cache.
 5. The machine of claim 4, wherein the input data and, or out data is generated by the data producer and read by a consumer, whereby the data producer and consumer are proximate a memory hierarchy due to the input data and, or out data held in the data buffers residing in the on-chip cache.
 6. The machine of claim 1, wherein the commands are written into the command buffer by the data producer and the commands are read by a consumer.
 7. The machine of claim 6, wherein writing of informational control data comprises updating a write pointer in a context buffer by the data producer; and wherein reading of informational control data comprises processing a read pointer in the context buffer by the consumer.
 8. The machine of claim 7, wherein the context buffer is pre-fetched.
 9. The machine of claim 1, wherein the command buffer and data buffers utilize addressing that wraps to a beginning of the command buffer and the data buffers once an end has been reached.
 10. The machine of claim 1, wherein a size of the command buffer and the data buffers may vary.
 11. A system encoded as a set of machine-readable instructions stored on non-transitory machine-readable media, the system to employ re-circulating ring buffers to reduce computing power, said system further comprising instructions for implementing: at least a set of logical nodes, wherein said logical nodes are processed by a plurality of stages, connected together in an arbitrary topology; a command and data buffers residing in an on-chip cache, said command and data buffers further comprising any one of at least a control information, input and, or out data delivering temporary data between a stage and, or a logical node in an execution graph, such that any one of the control information, input, and, or out data between logical nodes need not be stored in memory; an on-chip buffer management module, said on-chip buffer management module comprising a write pointer queue and a read pointer queue coupled via a cache gauge, thereby managing buffer content and traffic; and based on the write pointer queue updates, direct compute resources to prepare for a data producer stall and, or buffer clear.
 12. The system of claim 11, wherein the read pointer queue alerts a cache gauge of an impending completion of a graph task and, or a maximum capacity of any one the recirculating ring buffer and the cache gauge updates the write pointer queue.
 13. A non-transitory, machine-readable media, for re-configuring a machine for increased efficiency in processing flow comprising steps of: reducing compute resources via a plurality of logical nodes being processed on plurality of stages, with defined properties and resources associated with each logical node; reducing a size of a command buffer and data buffers by having the command buffer and the data buffers hold only any one of a control information, input, and, or out data necessary to stream a temporary data between logical nodes in an execution graph; residing said command buffer and data buffers in an on-chip cache, such that any one of the control information, input, and, or out data between nodes need not be stored in memory; and stalling a data producer of the machine from writing any more control information into the command buffer upon the command buffer being full, preventing command buffer over-writing.
 14. The non-transitory machine of claim 13, wherein the non-transitory machine is re-configured for increased efficiency in processing flow. 